Floorplanning is the process of placing functional devices ("functions," also referred to as modules, elements, blocks, or functional blocks) on a chip (integrated circuit die), and allocating interconnection space among the, so as to minimize the actual chip area required to encompass such functions and their interconnections, and to maximize the probability that such interconnections can be routed within that area.
Related to the floorplanning process, and creating a competing need for chip area is the amount of input/output (I/O) space required by the functional devices. Bond pads (connection points to the die) and the relatively large driver/receiver circuits and static protection networks required for input and output connections require a significant portion of the perimeter area of an integrated circuit die (chip) and eat into the space available for placing other functional devices.
Prior to the floorplanning process itself, which involves the placement of functions on a chip, the chip's logic must be designed. Logic designers generally employ hierarchical design techniques to determine the appropriate selection and interconnection of logic and/or memory devices which will enable the chip to perform the desired function. These techniques involve describing the chip's functionality at various "levels of abstraction," ranging from the most general function performed by the chip to the precise functions performed by each logic and/or memory element on the chip.
Thus, a logic designer's hierarchy consists of N levels of functions, where N is an integer (N.gtoreq.1) representing the number of hierarchical levels of functionality in the chip, the first level being the chip itself, and where n is an integer (1.ltoreq.n.ltoreq.N) representing the level of any particular function in the hierarchy.
A "parent" function at the (n)th level of the hierarchy is defined as a plurality of (n+1).sup.st level "children" functions, each of which is a "child" function. For example, a microprocessor at the (n)th level might be defined as the parent of the following (n+1)st level children: an ALU, a series of registers, a bus and various other functions ( each of which may or may not have a plurality of (n+2)nd level children, and so on).
Each child function which is not also a parent function (i.e., which has no children) is referred to as a "terminal" (or "leaf") function. Each terminal function is connected to at least one other terminal function, such connection commonly being referred to as a :net." A series of nets, each of which defines a plurality of interconnected functions, is commonly referred to as a "net list."
Note that lower levels of the hierarchy are commonly denoted by successively higher numbers. Thus, while level 1 refers to the top (chip) level of the hierarchy, levels 2, 3, and 4 constitute successively "lower" levels of the hierarchy.
Automated techniques for floorplanning ("floorplanners") are known in the prior art and fall into three basic categories: (1) "flat" floorplanners, which attempt to minimize space at only one level (the "level" which is created when the hierarchy is flattened by omitting all but the terminal functions), by placing only terminal functions; (2) "top-automated" floorplanners, which automate the floorplanning process at only the top level by placing only second level functions; and (3) "hierarchical" floorplanners, which automatic the process of floorplanning by optimizing placement of functions at many levels (preferably, at all levels).
An example of a hierarchical floorplanner which operates at all levels of hierarchy is taught in Modarres et al. U.S. Pat. No. 4,918,614, issued Apr. 17, 1990 and assigned to LSI Logic Corporation of Milpitas, Calif., incorporated herein by reference (hereinafter "Modarres"). Further references cited therein describe various "flat" floorplanners, and floorplanning related techniques.
Modern integrated circuits are generally produced by creating several identical integrated circuit dies at individual "die sites" on a single semiconductor wafer, then scribing (slicing) the wafer to separate (singulate, dice) the dies from one another. Generally, the dies are either rectangular or square. On the other hand, semiconductor wafers are generally round. The prior art die sites are defined by a series of parallel scribe lines which extend chordwise across the wafer, perpendicular to another series of chordwise parallel scribe lines.
Circuits and active elements on the dies are created while the dies are still together (un-singulated) on the wafer by ion deposition, electron beam lithography, plasma etching, mechanical polishing, sputtering, and numerous other methods which are well known to those skilled in the art of semiconductor fabrication. These processes are highly developed and are capable of producing extremely complicated circuits on the dies at a relatively low cost. However, the prior art method of fabricating square or rectangular "die sites" from a semiconductor wafer is impeding the development of complex integrated circuit dies. Problems with the prior art include (1) low wafer-layout-efficiency, E.sub.W, and (2) low die-topology-efficiency, E.sub.D.
According to the prior art fabrication of semiconductor devices on a wafer, a plurality of square or rectangular die sites are created on the face of a round semiconductor wafer. FIG. 1A is a diagram of the layout of prior art die sites on a semiconductor wafer. For simplicity of illustration, the wafer 104 in FIG. 1A is shown as being entirely round (circular in section). In practice, the wafer is usually provided with a "flat" extending chordwise from one circumferential point to another circumferential point located approximately ten degrees away from the one circumferential point. (This can be visualized by removing the five irregular die sites 120 located below (as viewed) the dashed line 122.)
FIG. 1A, illustrating the prior art fabrication of semiconductor devices by scribing a semiconductor wafer to define square or rectangular die sites, shows a plurality (thirty seven shown) of square die sites 102a through 102kk which have been created on the face of a round semiconductor wafer 104. These dies sites 102a . . . 102kk are termed "regular" die sites, since they will be used for integrated circuitry. A first series of scribe lines 106 and a second series of scribe lines 108 intersecting the first series of scribe lines 106, at a angle equal to ninety degrees, on the surface of the wafer 104, delineate one die from another, and ultimately determine the size and shape of the individual dies 102a . . . 102kk. Typically, all of the dies are fabricated in an identical manner to contain identical semiconductor circuits. Typically, the individual dies (chips) are connected to lead frames, or the like, and are packaged in some manner to interface with external (to the chip) systems or components.
It can be easily seen from the prior art that "regular" square dies 102 (102a . . . 102kk) are not geometrically obtainable around the periphery of the round wafer 104. (By way of analogy--square pegs simply do not fit neatly into round holes.) To the contrary, substantially entirely around the periphery of the wafer there are a number of "irregular" die sites 120, of various shapes and sizes, shown with dots (".multidot.") to distinguish the "irregular" die sites 120 from the "regular" die sites 102. These die sites 120 are irregular in that they typically are not used for the fabrication of integrated circuitry. Rather, the peripheral area of the wafer occupied by the irregular die sites 120 is simply discarded after the regular die sites 102 are singulated. The peripheral area of the wafer occupied by the aggregate of the irregular die sites 120 is referred to herein as "wasted real estate".
By way of illustrating the problems in the prior art, a wafer is usually on the order of 3-8, or more, inches in diameter, and the dies are usually square, having a side dimension on the order of one-eighth to one-half inch, or larger. The total wafer area is on the order of 14.5 square inches (for a four and three tenths inch wafer), and the area in which "regular" dies can be obtained is on the order of 9.25 square inches (37 square shaped dies, each die having area equal one quarter inch.sup.2). This can be expressed as a wafer-layout-efficiency "E.sub.W " on the order of 0.64 (regular die site area divided by wafer area). Evidently, in light of the non-trivial cost, time and effort that goes into making wafers, it would be desirable to increase this efficiency towards ONE. Hence, it can be seen that laying out (scribing) square dies on a round wafer will create a lot of wasted real estate.
Turning our attention from the shape of prior art square dies, to the topology of these individual dies, we see other problems.
Generally, as far as the present invention is concerned, there are two topological areas of interest on a given die:
1. An "active element area" containing active circuit elements, such as logic gates, interconnections between same, etc.; and PA1 2. An "I/O area" containing Input/Output (I/O) "bond pads", or the like, to which external connections will be made to the die, such as by wire bonding or by tape-automated bonding (TAB). PA1 1. Fitting (fabricating) as many active elements as possible in the active element area, to create more complex devices; and PA1 2. Fitting as many bond pads as possible in the I/O area, to accommodate increased numbers of connections to the device.
These two topological areas, in aggregate, account for the "total area" of the die and, generally, the I/O area surrounds the active element area.
The demands placed on modern integrated circuits are similarly headed in two directions:
These demands compete against each other, in the sense that more I/O area means less active area, for a given die size (e.g., total area), and vice-versa.
The active element area is typically located in a central portion of the die, with the I/O area surrounding the active element area. This appears to be "standard" methodology as driven by "standard" design rules.
A useful indicator of the size of active circuit elements is "line width, " which is essentially the size of the smallest conductive line that can be created on the die. Through advances in semiconductor fabrication technology, line widths in the sub-micron (&lt;1.0 .mu.m) range are already being achieved.
On the other hand, the size of bond pads is remaining relatively fixed and, more profoundly, relatively large vis-a-vis line widths. Bond pads are on the order of thousands of an inch. Thus, it is evident that bond pad developments are lagging the rapid development and increased utilization of the active element area, and result in an unfavorable I/O bond pad area:active element area ratio.
FIG. 1B shows an individual prior art square die 150, such as a die 102 (FIG. 1A), having four side edges 152, 154, 156 and 158. The die 150 has a total area (the length of a side squared), equalling the sum of a central active element area 160 and an I/O area 162 surrounding the active element area and extending to the four side edges of the die. The I/O area 162 is shown as the area outside of the dashed line 164. A plurality of bond pads 166 (only five of many shown) are disposed about the periphery of the die 150 in the I/O area 162. The active element area 160 contains circuit elements. A circuit element 168, illustrative of many circuit elements, is shown interconnected by lines 170 to the bond pads 166.
By way of a practical illustration of bonding wires to a die bond pad in the I/O area, the size of a die bond pad 166 is on the order of 0.004 inches (100 .mu.m), per side (bond pads are typically square), and the pads are spaced apart from one another on the order of 0.002 inches (50 .mu.m). For tape-automated bonding (TAB), the die bond pads are on the order of 0.002 inches (50 .mu.m), per side, and are spaced 0.002 inches (50 .mu.m). Also, a square die site typically has sides that are one half inches, total periphery of two inches, and a total area of one quarter inch.sup.2.
The I/O area 162 typically measures 0.010 inches wide, to allow for formation of the bond pads 166, and extends around the periphery of the die. Hence, for a square die having sides measuring one half inch, the active element area 160 will measure 0.480 inches by 0.480 inches.
Therefore, the geometric configuration of the prior art square die, having sides measuring one half inch, will result in approximately three hundred twenty nine bond pads (for external I/O connections to the die). This is not an uncommonly high number of I/O connections for a modern, complex semiconductor device. However, advances in complexity of integrated circuits has resulted in a great demand for increasing the number of bond pads in the I/O area.
Furthermore, the ratio of I/O area (162) to active element area (160) for the square die 150 is 0.085 (dimensionless). In other words, the amount of I/O area vis-a-vis the overall area can be expressed as a die-topology-efficiency "E.sub.D " and is 0.085 for this example of a prior art square die.
By way of summary, the prior art square die 150 of FIG. 1B (102, FIG. 1A):
(a) the "total area" is 0.2500 inch.sup.2 ;
(b) the "active element area" is 0.2304 inch.sup.2 ;
(c) the "I/O area" is 0.0196 inch.sup.2 ;
(d) the total periphery is 2.000 inches;
(e) number of bond pads is 329;
(f) die-topology-efficiency, E.sub.D is 0.085.
Because of the enormous disparity between die bond pad size and line width, and the increasing demand for I/O, the demand for I/O area is, in a sense, beginning to outpace the demand for active area and adversely offset the available active element area on a given die.
We see then, in general, that prior art square dies are not "efficient," in the sense that:
1. the geometric configuration of square dies result in low wafer-layout-efficiency "E.sub.W," thus creating "wasted real estate;"
2. square dies have a very low die-topology-efficiency "E.sub.D," limiting the number of bond pads that can be fabricated on the periphery of a die.
Further, with regard to the floorplanning process, we also see that the entire process of laying out integrated circuits produces "inefficient" results in that the competing demands of I/O area and functional area of a die are not well met.